Turn RTL into a checked chip layout.

teleon.dev/docs/silicon takes RTL through Verilator, Yosys and OpenROAD to a GDSII layout, with timing and DRC closure as the gate. Each run executes in a sandbox, and its checks run apart from the tools that made the layout.

v44.0teleon.dev/docs/siliconRTL to GDSIIhttpsjson

Read the docs Copy the agent prompt

One design, RTL to layout

RTL sourceuart_core, 200 MHz target

Verilatorlint clean, simulation passes

Yosys synthesis12,480 standard cells

OpenROAD place and routetiming met with 0.08 ns slack

Timing and DRC closureevery rule passes; GDSII stored in S220

Each stage hands its output to the next; the layout is released once timing and every design rule pass.

What it does

Simulate and lint

Verilator compiles the RTL into fast simulation models and lints it before synthesis.

Synthesize, place and route

Yosys maps the design to standard cells; OpenROAD places, routes and writes GDSII.

Close timing and DRC

A layout is accepted once every timing path and design rule passes.

The contract

A run request names the RTL source, the process kit and the clock target; the result is a GDSII layout with its timing and DRC reports.

ToolsVerilator, Yosys, OpenROAD

OutputGDSII layout

GateTiming and DRC closure

StoreS220 RTL and physical design runs

Identifiers

GDSII
teleon_extensible_evaluations

Execution contracts

Request and responseCopy

POST /v1/silicon/runs
Host: api.teleon.dev
{
  "rtl": "swh:1:cnt:41c8...e2",
  "top": "uart_core",
  "pdk": "open_130nm",
  "clock_mhz": 200
}

# Response
{
  "run": "si_5120",
  "cells": 12480,
  "timing": {"met": true, "slack_ns": 0.08},
  "drc": "clean",
  "gds": "swh:1:cnt:0b7e...5d"
}

Endpoints

Method	Path	Access	What it does
`POST`	`/v1/silicon/runs`	RING-2	Start an RTL-to-GDSII run
`GET`	`/v1/silicon/runs/{id}`	RING-2	Read timing, DRC and stage logs
`GET`	`/v1/silicon/runs/{id}/gds`	RING-2	Download the GDSII layout

Listed paths appear in the service’s published files today. This surface comes from the Teleon Omnibus Codex v1.0 to v50.0, Oct 25, 2026. In the one-host plan every path here is served under api.teleon.dev/v1/silicon.

How it connects

Reads from

Workersteleon.dev/docs/workers Verification sandboxteleon.dev/docs/sandbox Files and vaultteleon.dev/docs/files

Feeds into

Content storeteleon.dev/docs/cas Assurance and evidenceteleon.dev/docs/assurance

Queuesaq651-aq700

StoresS220 RTL and Physical Design Runs

For agents

Give your agent the read-only guide first. It reports back before any write.

Agent prompt

Read https://teleon.dev/docs/silicon.md and describe the stages of an RTL-to-GDSII run. Read only.

Copy

llms.txt Agent card

Words on this page

Full glossary

RTL: Register-transfer level: a hardware description, in a language such as Verilog, of how data moves between registers each clock cycle.
GDSII: The standard file format for a chip's final layout geometry, the file a foundry builds from.
DRC: Design rule check: confirms a layout meets the foundry's spacing, width and density rules.